This invention relates to stacked paired die packages, and more particularly to a stacked paired die package with dies stacked back to back.
Semiconductor wafer manufacturing is a lengthy process. Once the functional design has been configured into a product, it requires a redesigned of the product if additional functionality needs to be added. For example, going from a 256 MB chip to a 512 MB chip may require changes to both the semiconductor fabrication processes and the chip design. Similarly, going from a 32-bit to a 64-bit processor may require similar changes involving both fabrication processes and chip design. The conventional method of improving functionality and performance is utilizing the substrate for connectivity, attaching multiple components to the same substrate. A variety of multi-component and/or stacked die designs are known to those skilled in the art.
A semiconductor die package design incorporating at least a pair of functional semiconductor dies. The input/output pads locations on one of the dies (the daughter die) are located so as to be the near mirror image of the original die (mother die). The package architecture includes two dies back-to-back or stacked dies back-to-back, therefore a plurality of input/output interconnections can be formed. The package increases density and performance by twofold or more compared to a regular package containing only one die with the same footprint. At least one additional pin can be dedicated as the chip select pin for the daughter die or multiple dies. The other pins can be shared with the mother die.